From 1693185272d9f4d71135f21ab443b5cd8fdfad48 Mon Sep 17 00:00:00 2001 From: Keir Fraser Date: Wed, 5 Jan 2011 09:52:18 +0000 Subject: [PATCH] x86: Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS Allow dom0 to write MSR IA32_ENERGY_PERF_BIAS There is a new hardware feature, which lets system software to set Energy Performance Preference. This is a opaque knob in the form of IA32_ENERGY_PERF_BIAS MSR, which has a 4 bit Energy Performance Preference Hint. The support for this feature is indicated by CPUID.06H.ECX.bit3. Refer to Intel Architectures Software Developer's Manual for more info. Let dom0 tools to control it. Signed-off-by: Wei Gang --- xen/arch/x86/traps.c | 1 + xen/include/asm-x86/msr-index.h | 1 + 2 files changed, 2 insertions(+) diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c index 0c4b5441d7..ad4231cec4 100644 --- a/xen/arch/x86/traps.c +++ b/xen/arch/x86/traps.c @@ -2333,6 +2333,7 @@ static int emulate_privileged_op(struct cpu_user_regs *regs) goto fail; break; case MSR_IA32_THERM_CONTROL: + case MSR_IA32_ENERGY_PERF_BIAS: if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ) goto fail; if ( (v->domain->domain_id != 0) || !v->domain->is_pinned ) diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index cc32932cd4..316a1931cd 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -330,6 +330,7 @@ #define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1<<23) #define MSR_IA32_TSC_DEADLINE 0x000006E0 +#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 /* Intel Model 6 */ #define MSR_P6_EVNTSEL0 0x00000186 -- 2.30.2